dual operational atplifier description t h e JRC4558 i s a m onoli t hi c in t egra t e d c ir c uit designed for dual operational amplifier. featnres *no frequency compensation required. *no latch-up *large commom mode and differential voltage range *parameter tracking over temperature range *gain and phase match between amplifiers *internally frequency compensated *low noise input transistors dip-8 sop-8 block diagram vcc vee in(-) in(+) output 1 2 3 4 8 7 6 5 out2 in2(-) in1(+) vee vcc out1 in1(-) in2(+) absolnte maximnm ratings characteristic sy bol value unit supply voltage vcc 22 v differential input voltage v i(diff) 18 v power dissipation p d 400 mw input voltage v i 15 v operating temperature t opr 0~+70 c storage temperature t stg -65~+150 c JRC4558 linear integrated circuit 1 free datasheet http:///
electrical characteristics ( ta=25 c ,vcc=15v,vee=-15v) characteristic sy bol test condition min typ. max unit supply current icc 3.5 5.6 ma input offset voltage v io rs<10k w 26mv input offset current i io 5 200 na input bias current i bias 30 500 na large signal voltage gain gv vo(p-p)=10v,r l <2k w 20 200 v/mv commom mode input voltage range v i(r) 12 13 v commom mode rejection ratio cmrr rs<10k w 70 90 db supply voltage rejection ratio psrr rs<10k w 76 90 db output voltage swing vo(p-p) r l >10k w 12 14 v power comsumption pc 70 170 mv slew rate sr vi=10v,r l >2k w ,c l <100pf 1.2 v/ m s rise time t ris vi=20mv,r l >2k w c l <100pf 0.3 m s overshoot os vi=20mv,r l >2k w ,c l <100pf 15 % typical performance characteristics 10 10 2 10 36 10 fig.3 power bandwith(large signal swing vs frequency) output voltage (v) frequency (hz) 10 4 10 5 0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 fi g .1 positive output volta g eswin g vs load resistance load resistance ( ) 10 2 10 4 10 5 10 3 1.0 3.0 5.0 9.0 11.0 13.0 15.0 7.0 output voltage (peak) (v) fi g .2 positive output volta g eswin g vs load resistance output voltage (peak) (v) load resistance ( ) 10 2 10 4 10 5 10 JRC4558 linear integrated circuit 2
0 20 40 60 80 100 120 140 fig. 7 spectral noise density input noise(nv/hz) frequency hz) 10 100 10 5 10 3 10 4 10 6 gv=10 rs=100k 10 10 2 10 36 10 10 -1 1 10 fig. 6 output noise vs rs output noise(rms) (mv) rs ( ) 10 4 10 5 10 -2 gv=1000 gv=100 gv=10 gv=1 10 10 2 10 3 6 10 fig. 4 burst noise vs rs input noise(peak) (mv) rs ( ) 10 4 10 5 1 10 10 2 10 3 bw=1.0hz to 1.0khz 10 10 2 10 2 6 10 fig. 5 rms noise vs rs input noise(rms) ( v) rs ( ) 10 4 10 5 0.1 1 10 10 3 0 20 40 60 80 100 120 140 fig. 8 open loop frequency response frequency hz) avd ( db) -20 10 100 10 5 10 3 10 4 10 6 110 7 10 100 10 5 10 3 10 4 10 6 110 7 frequency hz) fig. 9 phase margin vs frequency phase margin 0 20 40 60 80 100 120 140 160 180 JRC4558 linear integrated circuit 3
package dimensimns 8-dip-p-300 6.40 2.54 1.25 9.20 3.40 5.08 3.30 7.62 0.25 15 degree 0.46 8-sop-p 6.00 3.95 5.72 1.95 5.13 4.92 1.27 0.41 JRC4558 linear integrated circuit 4
|
